Combined transmit filter and D-to-A converter

ABSTRACT

A combined filter and digital-to-analog converter (DAC) provides an integrated apparatus for converting a digital data stream into a filtered analog signal. The combined filter/DAC implements an N-tap digital filter using a serial shift register whose register output taps interconnect with a resistive ladder network. Each input to the resistive ladder has a specific signal attenuation (weighting factor) with respect to a ladder output node. Each ladder input&#39;s weighting factor corresponds to one of the digital filter tap coefficients. Shift register output taps interconnect with ladder network inputs in an arrangement that matches each output tap to its required weighting factor. With the resistive ladder, very small weighting factors can be realized without using large-value individual resistors that are problematic in high-bandwidth circuits. The filtered analog signal is taken from the ladder&#39;s output node and represents the weighted summation of tap outputs. By dividing the data bits input to the shift register into M phases, the N-tap filter/DAC may be realized in an N/M (L) length shift register. Each of the L taps is associated with a different group of M resistors. For each of the M phases, the L taps connect to a different one of the M resistors. Thus, only N/M resistors are driven at any one time, thereby reducing power consumption. This switching scheme may be combined with the ladder network arrangement above to reduce power and avoid the use of large-valued resistors.

FIELD OF THE INVENTION

The present invention relates generally digital-to-analog (D-to-A)conversion and signal filtering, and more particularly to a combinedD-to-A converter and transmit filter for a digital radio communicationdevice.

BACKGROUND OF THE INVENTION

Modern mobile communication devices often use digital modulationtechniques. Digital modulation offers many advantages over analogmodulation, such as greater noise immunity and greater robustness to theadverse conditions of the communication channel. Digital modulationaccommodates digital error detection and correction codes that candetect and correct errors that occur in transmission. Digital modulationalso allows use of various digital signal-processing techniques, such assource coding, encryption, and equalization that improves the overallperformance of the communication system.

In a digital communication system, the modulating signal (i.e. theinformation transmitted) is represented as a time sequence of symbols orpulses. Each symbol has one of afinite number of states. There are 2^(n)possible states where n is equal to the number of bits per symbol. Themodulating signal is impressed onto a carrier waveform by varying acharacteristic of the waveform. For example, in amplitude modulation,the amplitude of the carrier waveform is varied linearly with themodulating signal. In phase modulation, the phase of the waveform isvaried linearly with the modulating signal. In complex modulation, alsoknown as quadrature modulation, variations in both the amplitude andphase of the carrier waveform occur and thus create a time-varyingsignal vector in the two-dimensional complex plane.

FIG. 1 is a block diagram of a balanced quadrature modulator of theprior art, which is indicated generally by the numeral 10. A digitalsignal processor (DSP) 12 generates symbol sequences corresponding tothe I and Q components of a modulating signal. The symbol sequencescorrespond to the real and imaginary parts of a desired complexmodulation. The real part is given by the desired amplitude times thecosine of the desired phase angle. The imaginary part is given by theamplitude times the sine of the desired phase angle. Digital-to-analog(D-to-A) converters 14 convert each symbol sequence into an analogwaveform, referred to as I (In-phase) and Q (Quadrature) modulatingwaveforms. Filters 16 remove smooth step changes in the I and Qwaveforms that result from sampling and quantization. Absent filtering,the step changes in the modulating waveforms could produce undesirablespectral components in the transmitted signal that would interfere withadjacent radio channels. Filters 16 are typically low-pass filters thatpass desired components of the modulating signal while suppressinghigher frequency components associated with step changes in themodulating waveform. After filtering, the I and Q modulating waveformsare passed to a quadrature modulator 18, which impresses the modulatingwaveforms onto a carrier waveform.

It is known in the prior art that filtering may be performed usingFinite Impulse Response (FIR) filters, which perform a weighted sum overa sliding window of successive symbols. Recent innovations in FIRfilters are disclosed in U.S. Pat. No. 5,867,537 to Dent, which isincorporated herein by reference. The '537 patent discloses a method offiltering a bit sequence using a shift register and resistor networks toimplement the weighting coefficients of the transmit filter. Balanced Iand Q signals are input to a shift register at the bit rate or a desiredoversampling rate. The non-inverted and inverted outputs of each shiftregister stage are connected to identical first and second resistornetworks. The first and second resistor networks comprise a plurality ofresistors of different value representing the desired transmit filterweights. The non-inverted outputs of the shift register are used forpositive weights and the inverted outputs are used for negative weights.A first group of the non-inverted and inverted outputs is connected tothe first resistor network and a second complementary group ofnon-inverted and inverted outputs are connected to the second resistornetwork. Thus, the first and second resistor networks producecomplementary I or Q outputs suitable for input to a balanced quadraturemodulator.

One drawback to using resistive networks to perform filtering is thatlarge resistor values are needed to implement small weighting factors.Therefore, there is a need for further improvements in FIR filters.

SUMMARY OF THE INVENTION

The present invention is a combined digital to analog converter andtransmit filter for use in a quadrature modulator. According to thepresent invention, a transmit filter is constructed by using a combiningnetwork, such as a resistor network, connected to the taps of a shiftregister to provide desired tap weights. To avoid using excessively highresistor values to implement very small weights, a ladder network isused to attenuate the contribution from taps with small associatedweight values. However, a ladder network may only provide aprogressively increasing attenuation from one stage to the next. Inorder to facilitate the use of a ladder network therefore, the inventioncomprises, in a first aspect, sorting of the filter tap weights in orderof absolute magnitude in order to determine a modified order in whichthe taps of the shift register must be connected to successive sectionsof the ladder network. In a second aspect of the invention, a filterthat operates at an oversampling factor of L samples per bit period orchip period is constructed by first separating the N tap weights into Lgroups of N/L weights, each group corresponding to one of the Loversampling phases. A resistor network is then designed for each groupof N/L taps, which are provided by a shift register of length N/L stagesand clocked at the chip rate or bit rate. A higher frequency clock of Ltimes the chip or bitrate controls progressive selection among the Lresistor networks of the network that is to be connected to the shiftregister to provide the output for each of the L oversampling phases.

A third aspect of the invention comprises a combination of the first andsecond aspects described above. After separating the N tap weights intoL groups of N/L weights, each group of L tap weights is sorted in orderof absolute magnitude and a ladder network for each group providesprogressive attenuation of the contribution from successive taps in thesorted order of each group. An array of switches is controlled by anoversampling clock of L times the chip rate or bit rate to determinewhich ladder network shall be driven by the shift register outputs toprovide the filtered signal output for each phase.

According to a fourth aspect of the invention, when the ladder networksfor two or more oversampling phases comprise the same resistor valuesand differ only in the order in which the taps are connected tosuccessive ladder network sections, the filter may be simplified to asingle copy of the ladder network combined with a selection switch toselect the different order in which the shift register taps areconnected to the ladder network for different sampling phases.

According to a fifth aspect of the invention, a balanced output from thefilter may be provided for driving a balanced modulator by duplicatingthe resistor networks, connecting the duplicate networks to registeroutputs of the opposite polarity to those connected to the primarycopies of the resistor networks.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a conventional quadrature modulator.

FIG. 2 is a schematic diagram of a converter/filter using a shiftregister and resistive networks to weight the outputs of the shiftregister.

FIG. 3 is a schematic diagram of a converter/filter using a shiftregister and resistive ladder networks.

FIG. 4 is a schematic diagram of a ladder illustrating a method forcomputing resistor values.

FIG. 5 a schematic diagram of an exemplary ladder network for theconverter/filter of the present invention.

FIG. 6 is a schematic diagram of a converter/filter of the presentinvention using a switched resistor network.

FIG. 7 is a schematic diagram of a switch used in the embodiment of FIG.6.

FIG. 8 is block diagram of a complete converter/filter constructed inaccordance with the present invention, making use of the switch resistornetwork illustrated in FIG. 6.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 2 is a schematic diagram of a combined D-to-a converter andtransmit filter 20 for a quadrature modulator according to U.S. Pat. No.5,867,537 to Applicant. The converter/filter 20 implements an N tapfinite impulse response filter using N tap weights. Separate filters areused for the I and Q channels. Only one filter 20 is shown in FIG. 2.

An I or Q bit stream enters a memory device having a plurality of memoryelements for receiving and holding signal sample values. In thedisclosed embodiments, the memory device comprises a shift register 22having N shift register stages 24. Each shift register stage 24comprises a flip-flop having complementary non-inverted Q and invertedoutputs {overscore (Q)}. To implement oversampling, the spacing betweenoutputs or taps may be less than the bit rate or chip rate. For example,the taps of the shift register stages 24 may be spaced one-fourth of thechip period to implement an oversampling factor of four.

The non-inverted and inverted outputs in each stage of the shiftregister 22 connect to first and second resistor networks 30, 40. Theresistor networks 30, 40 comprise, in the disclosed embodiments of U.S.Pat. No. 5,867,537, a plurality of weighting resistors 34, 44 disposedin parallel branches 32, 42 of the resistor networks 30, 40. There is aone-to-one correspondence between branches 32, 42 in resistor networks30, 40 and stages 24 in the shift register 22. The parallel branches 32,42 are connected at one end to one of the inverted or non-invertedoutputs of the shift register 22. The opposite end of each branch 32, 42is connected to a summing node 36, 46. In a stage where a non-invertedoutput of the shift register 22 connects to a branch 32 the firstresistor network 30, the non-inverted output connects to a correspondingbranch 42 the second resistor network 40 and vice versa. Thus, theweighted outputs of summing nodes 36 and 46 will be balanced outputssuitable for input to a balanced modulator such as described in U.S.Pat. No. 5,530,722 to Applicant, which is incorporated herein byreference. The weighted outputs will swing in antiphase about acenterline of Vcc/2.

The conductance values G₁ to G_(N) of weighting resistors 34 and 44 aregiven by the desired filter impulse response, which is the inverseFourier transform of the desired filter frequency response. When theideal frequency response is finite, such as a root-raised cosineresponse in the frequency domain, the impulse response obtained bytransforming from the frequency domain to the time domain will beinfinite in extent. Thus, the impulse response should be truncated to afinite number of N stages so as to minimize spectral sidelobes caused bytruncation, as is well-known in the art. In the above example using FIG.1, the repetition of each chip four times also imposes an extra sin(x)/xfactor in the frequency response which must be accounted for by firstdividing the desired frequency response by the sin(x)/x factor. This isavoided in one embodiment of the invention discussed below.

When a weight value is negative, the corresponding weighting resistor34, 44 connects to an inverted output of the shift register 22.Likewise, when weight value is positive, the corresponding weightingresistor 34, 44 connects to an uninverted output. If imaginary orcomplex values are needed, weighting resistors 34, 44 of the I filterconnect to the Q shift register and vice-versa. Thus it is possible toimplement any weight values, +ve, −ve, real, imaginary or complex.

For an I and a Q filter, both balanced, there are 2N resistors connectedto non-inverted and inverted outputs which are instantaneously at anoutput voltage level corresponding to the 1-level of Vcc and the other2N are connected to non-inverted and inverted outputs at the 0-level orground voltage. The total resistance from Vcc to ground is thus given bytwo of the 2N sets of weighting resistors 34, 44 in series and the totalcurrent power consumption is Vcc divided by the net value of one set ofN weighting resistors 34, 44 connected in parallel. To reduce the powerconsumption, high resistor values are therefore desirable. For example,assuming Vcc=3 volts and 3 mA is the target power consumption, the sumof G1+G2+G3 . . . G_(N) should be 1 mhos or a resistance of 1 KOhms. ForN=128 taps, the average resistance value is then 128 KOhms, which is ahigh value to fabricate on a chip using polysilicon or diffusionresistors. Long FETs, biased ON, are a known alternative way of makinghigh-value resistors on a CMOS chip. However, all “on-chip” resistorshave a wide absolute value spread, but fortunately it is only therelative values G1:G2:G3 . . . that determine the filter frequencyresponse, and resistor ratios are held much more accurately on chip thanare absolute values.

When the coefficient value spread is large, this will also result in theneed for resistances that are much higher than the average value of 128KOhms. A disadvantage of high-value resistors is that parasiticcapacitances can become significant for filters of wide bandwidth.Therefore, there is an interest in finding ways to reduce resistorvalues without increasing power consumption, and also an interest infinding ways to implement small coefficients without excessive resistorvalues.

Referring now to FIG. 3, a combined N-tap filter/D-to-A converter of thepresent invention is shown therein and indicated generally by thenumeral 100. In the example of FIG. 3, the converter/filter is depictedhaving 14 taps (N=14), but greater or fewer taps may be used dependingupon the application. Separate converter/filters 100 are used for the Iand Q channels. An I or Q bitstream enters a serial shift register 102having 14 shift register stages 104. Each shift register stage 104comprises a flip-flop and includes a positive logic output 106 (Q) and anegative logic output 108 ({overscore (Q)}). The Q/{overscore (Q)}outputs from the shift register 102 are termed taps, with the {overscore(Q)} taps 108 forming the logical complement to the Q taps 106. Theinput clock frequency relative to the incoming data chip rate (or bitrate) determines the tap spacing between the shift register stages 104.In this example, the CLK signal input to shift register 102 is fourtimes the chip rate of the incoming I or Q channel data and, therefore,the tap spacing is one-fourth of the chip period and thefilter/converter 100 operates with an oversampling factor of four. Thus,the input stream ‘1010’ becomes ‘1111000011110000’ with oversampling,which represents a square wave.

Resistive ladder networks 110 and 130 provide signal attenuation foreach of the N-tap outputs 106 and 108 from shift register 102 inaccordance with the weighting factors required for the N-tap filter, asdetermined from the N filter coefficients. Ladder network 110 comprisesa set of branch inputs 122 all feeding into a ladder output connection116, with each branch input 122 having potentially different weightingcharacteristics. Branch circuits 118 connect corresponding branch inputs122 to a series resistive circuit 112 comprising a plurality ofweighting resistors 114. Each branch circuit 118 connects the externalsignal received at the branch input 122 to a different node or stage inthe series resistive circuit 112 through a weighting resistor 120.Resistive ladder networks 110, 130 provide increasing signal attenuationfor external signals applied to branch inputs 122 successively furtheraway from the ladder output connection 116. For example, assuming thatall weighting resistors 120 in the branch circuits 118 are of equalvalue, a signal applied to the branch input 122 numbered “1” in FIG. 3will have greater attenuation than a signal applied to the branch input122 numbered “14.” The extent to which the attenuation varies betweenany two given branches or stages depends upon the accumulated resistancebetween the two nodes in the resistive circuit 112 where the two givenbranch circuits 118 connect.

Ladder network 130 is similarly constructed having a series resistivecircuit 132 with series weighting resistors 134, a set of branch inputs142 providing connectivity between externally applied signals and theseries resistive circuit 132 through branch circuits 138, each branchcircuit 138 having a weighting resistor 140.

The N Q/{overscore (Q)} output taps 106 and 108 from shift register 102interconnect with the branch inputs 122 and 142 of ladder networks 110and 130 in a pattern determined by the tap weighting (signalattenuation) required for any given shift register 102 output tap.Because of the progressive attenuation nature of the resistive laddernetworks, tap outputs from shift register 102 that require the smallestweighting (greatest attenuation) are connected furthest from the ladderoutput connection points 116 and 136 for the ladder networks 110 and130. According to the present invention, the filter tap coefficients orweighting factors implemented by the filter are sorted in ascendingorder of absolute value and a ladder network is constructed thatimplements the weighting factors in the sorted order. The registerstages 104 of the shift register 102 connect to the branches 122, 132 ofthe ladder networks 110, 130 in order of absolute magnitude of thecorresponding tap coefficient. That is, the shift register stage 104with the smallest tap weight (i.e. the highest resistance) connects tothe first branch input 122 and the shift register stage 104 with thelargest tap weight (i.e. the smallest resistance) connects to the lastbranch input 122. In between, the shift register stages 104 connect tocorresponding branch inputs 122 in ascending order of tap weights. Theladder networks 110, 130 provide decreasing resistance from the firststage to the last stage so that small weighting factors can beimplemented without excessively large resistor values.

Further, to maintain a balanced output, if a Q output 106 from a givenshift register stage 104 connects to the third branch input 122 ofladder network 110, then the {overscore (Q)} output from that same givenshift register stage 104 connects to the third branch input 142 ofladder network 130. Thus, the weighted outputs 116 and 136 of seriescircuits 112 and 132, respectively, will be balanced outputs suitablefor input to a balanced modulator. The weighted outputs will swing inantiphase about a centerline of Vcc/2. Note that either resistive ladder10 or 130 may interconnect with both Q and {overscore (Q)} outputs fromthe shift register 102, with the specific interconnection determined bythe sign and magnitude of the original N-tap filter coefficients.

As an example of ordering in accordance with tap weighting values,assume the following set of 14 tap weights:

W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 0.01 0.03 −0.08 −0.15−0.1 0.3 0.5 0.5 0.3 −0.1 −0.15 −0.08 0.03 0.01

In order of absolute magnitude, the tap weights are as follows:

W1, W2, W3, W5, W4, W6, W7, W14 W13 W12 W10 W11 W9 W8 0.01 0.03 0.08 0.10.15 0.3 0.5

Like weights have been grouped together. Because of symmetry in thisexample, the right and left halves of the ladder network are identicaland comprise conductances G1 to G7 and resistances R1 to R6 to be foundin order to satisfy the requirement that the admittance matrix elementsin the row corresponding to the output node shall be in proportion tothe absolute magnitude of the desired weights W1 to W7 (W8 to W14).Since there are 13 degrees of freedom and only seven weights, the othersix degrees of freedom (the 6 resistors R1 to R6) can be used tominimize some combination of power and chip area or to simplify thedesign. For example, all the values G1 to G7 could be made equal and thevalues R1 to R6 chosen to get the desired weight distribution.

FIG. 4 illustrates the method of designing ladder networks with allinput conductances equal to G_(O). Imagine a movable short-circuit, asshown connected to the right-hand side of R_(M). The proportion of thecurrent I flowing to ground that comes from voltage source V_(m) and theproportion coming from V_(M−1) is in the ratio of coefficients C_(M) toC_(M−1) where the coefficients C₁ to C_(M) are magnitudes sorted indescending order (i.e. C_(M) is the smallest coefficient and C₁ is thelargest). Thus, the relationship between the input conductance G_(O) andresistances R_(m) is expressed as follows:

G _(O)/(1+G _(O) R _(M)): G _(O) =C _(M) :C _(M−1)  Eq.(1)

which can be rewritten as:

 R _(m−1)=(C _(M−1) /C _(M)−1)/G ₀  Eq.(2)

We now imagine moving the short-circuit one place to the right, to theright-hand side of R_(M−1). The voltage sources V_(M) and V_(M−1) arealso now considered to be of the same sign so that their expectedcontribution is in proportion to the sum of the coefficient magnitudesC_(M)+C_(M−1). This contribution arises through the impedance of G_(O)in parallel with G_(O) in series with R_(M), expressible as a newconductance value.

G _(O) ′=G _(O) +G _(O)/(1+G _(O) R _(M−1))  Eq. (3)

When R_(M−2) is added in series, the contribution from V_(M) and V_(M−1)will be proportional to G_(O)′/(1+G _(O) ′R _(M−2)) while thecontribution to the current I from V_(M−2) is proportional to G_(O).These should be in the ratio (C_(M)+C_(M−1)) to C_(M−2)′ thereforegiving:

R _(M−2)=(1/G _(O))C _(M−2)/(C _(M) +C _(M−1))−(1/G _(O)′)  Eq. (4)

We now combine G_(O)′ in series with R_(M−2) and then in parallel withthe G_(O) that connects to V_(M−2) to get a new value of G_(O)′, andthen by similar reasoning obtain:

R _(M−3)=(1/G _(O))C _(M−3)/(C _(M) +C _(M−1) +C _(M−2))−(1/G_(O)′)  Eq. (5)

and so forth until all values R_(i) are determined. A final calculationof G_(O)′ gives the output conductance of the ladder.

The above calculations may be done manually for smaller ladder networksbut are more practically implemented as a computer program. Using such acomputer program, a set of tap weights (resistors) corresponding to agiven filter design were determined for an exemplary 13-tap combinedfilter/converter in accordance with the present invention. The tablebelow provides the resistive data used to construct the filter/converter500 shown in FIG. 5.

Tap Tap Logical Admittance Resistance Resistor # Output (G) mhos (R)Ohms Designator  1 Q 0.0001 465.1 R1 12 {overscore (Q)} 0.0001 5357.1 R2 4 {overscore (Q)} 0.0001 774.4 R3 11 {overscore (Q)} 0.0001 573.2 R4 13Q 0.0001 1134 R5  2 {overscore (Q)} 0.0001 806.5 R6  3 Q 0.0001 458.5 R710 Q 0.0001 204.9 R8  9 {overscore (Q)} 0.0001 94.4 R9  5 {overscore(Q)} 0.0001 6697.4  R10  6 Q 0.0001 1250.2  R11  7 Q 0.0001 Note thatthe filter coefficient corresponding to Tap 8 is zero in this exampleand does not contribute to the output.

The combined filter/converter 500 of FIG. 5 provides 12 branch inputs122 for 13 tap outputs, Q1/{overscore (Q)}1 through Q13/{overscore(Q)}13 of an associated shift register 510—Q8 is skipped because of itsassociated zero weighting coefficient. Note that each branch circuit 118individually connects through an admittance G1 to G12 of 0.1 mmho({fraction (1/10)} Kohms) to successive nodes in a series of resistorsR1 to R11. The ladder network 500 provides an output connection point520 that represents the summation of inputs Q1 through Q13 from shiftregister 510, with each of the Q input signals being weighted inaccordance with the attenuation associated with the individual branch orstage to which it is applied. The ladder network 500 shown in FIG. 5allows implementation of small tap weights without using largeresistors, but is not optimized for minimal power consumption. Thereforethere is still an interest in defining a combined filter/converterhaving reduced power consumption.

FIG. 6 shows an alternate embodiment of the combined converter/filter ofthe present invention indicated generally by the numeral 600. Theresistive networks 610 and 620 are not configured as ladder networks inthis embodiment of the present invention. FIG. 6 assumes that the I or Qdata stream input to shift register 602 comprises a series of impulsesdelivered in succession at the chip or bit rate of the I or Q datastream, rather than a series of square waves assumed in the earlierexamples given. FIG. 6 further assumes that the shift register 602 isclocked at the chip or bit rate of the input I or Q data stream. While asquare wave signal is assumed to maintain its logical value for thewhole chip period, an impulse signal is active for only the firstportion of each chip or bit period and has a zero value otherwise. Thus,the square wave input I or Q bit stream discussed earlier produced‘111100001111000’ when sampled at four times the chip or bit rate, whilethe waveform considered for FIG. 6 is 1000000010000000 . . .

In the earlier example, the shift register was clocked four times fasterthan the chip or bit rate of the incoming I or Q data. Assuming now thatthe earlier example's input data really comprises a series of impulsesrather than square waves, the input signal (impulse) is active duringonly the first one of every four clock pulses. This causes the shiftregister of the earlier example to shift through only one meaningful bitfor every four register stages, the other three stages containingnon-data zero samples—the sampled impulse input is active only everyfourth clock pulse. Changing from Boolean notation to arithmeticnotation, the input stream in the earlier square wave example, now animpulse input, becomes ‘1000-10001000-1000’ where a ‘1’ represents thevalue of a Boolean ‘1’, ‘−1’ represents the value of a Boolean ‘0’, and‘0’ represents non-data and has no contribution from the tap to thefilter output. Therefore, when the I or Q input data is a stream ofimpulses delivered at the chip rate, only ¼ of the earlier illustratedshift register's taps contribute to the output signal from the laddernetwork at any given time. This situation is more thoroughly illustratedin the example below:

Bit 1 Bit 2 Bit 3 Bit 4 1 0 1 1 Original I or Q CK CK CK CK CK CK CK CKCK CK CK CK CK CK CK CK Boolean Input Bitstream 1 2 3 4 5 6 7 8 9 10 1112 13 14 15 16 4x Sampling Assuming 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1Square-Wave Data 4x Sampling Assuming 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0Impulse Data Arithmetic Representation 1 0 0 0 −1 0 0 0 1 0 0 0 1 0 0 0Note: CK = clock pulse input to the serial shift register.

Thus, looking at the arithmetic representation of the last row in thetable above, the shift register contents through four clock cycles(assuming four times oversampling) appear as follows:

SHIFT REGISTER STAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK 1 1 0 00 −1 0 0 0 1 0 0 0 1 0 0 0 CLK 2 0 1 0 0 0 −1 0 0 0 1 0 0 0 1 0 0 CLK 30 0 1 0 0 0 −1 0 0 0 1 0 0 0 1 0 CLK 4 0 0 0 1 0 0 0 −1 0 0 0 1 0 0 0 1

Because the shift register is being clocked at four times the chip orbit rate, the clock signal may be thought of as effectively having fourchip-rate clock signals, with each of the four clock signals having asuccessive offset of ¼ the chip period. Thus, a chip period may be saidto have four phases, corresponding to the four effective chip rate clocksignals. At each of these four “phases”, only one quarter of the tapscontributes to the output.

The converter/filter 600 of FIG. 6 takes advantage of the fact that only¼ of the N-tap outputs from the shift register actually contribute tothe ladder network output in order to reduce power consumption. FIG. 6assumes a 52-tap filter implementation is required (N=52). In FIG. 6,the shift register is implemented with N/4 or 13 register stages, ratherthan 52 register stages seemingly required. This is possible because the13 taps of shift register 602 effectively connect to a different pair ofresistor networks for each of the four phases of the I or Q chip period.This is accomplished through the set of switches 630. The followingexplanation applies to resistor network 610 and 620. Where a referencenumber for resistor network 610 is given, the corresponding referencedesignator from resistor network 620 follows enclosed in parenthesis.Each Q and {overscore (Q)} tap output from the shift register 602connects to one resistor within one of four groups of resistors 616(626). These four groups of resistors 616 (626) connect to a summingnode 618 (628) through branch connections 614 (624). For each of thefour phases comprising a single chip period, the 4-pole switches 630 allassume a like position and connect the Q and {overscore (Q)} tap outputsfrom shift register 602 to the summing node 618 (628) through a specificone of weighting resistors 616 (626).

This is accomplished by clocking the switches synchronous with thechip-period clock driving the shift register 602, but at four times therate. In this manner, each of the 13 output taps from the shift register602 has four possible weighting factors, one for each of the four chipperiod phases. For example, in the first group of branches (G11 throughG14), the switch 630 connects to the register output tap from shiftregister 102 to G11 for ¼ the chip period, then to G12 for the next ¼period, and so on through to G14. The other switches 630 associated withthe other groups of branches function similarly.

Thus, the 13-tap shift register 602 of FIG. 6 realizes the functionalityof a 52-tap (4 phases×13 taps=52 effective taps), but saves power versusa straightforward 52-tap implementation by only having to power ¼ thenumber of resistors at any one time. With the arrangement shown in FIG.6, it may be advantageous to stagger the clock phase that controlsrotation of switches 630 such that a gradual switch-over from oneresistor subset to the next occurs, effectively interpolating thewaveform to more than four samples per chip equivalent. This also avoidsall the switching glitches occurring at the same time. The switches 630may be implemented using transistors, and may be advantageouslyimplemented as complementary pairs of N-channel and P-channelmetal-oxide-semiconductor field-effect-transistors (MOSFETS).

Although groups of four resistors are shown connected to the same 4-poleswitch 630 (i.e. all to a non-inverting Q output or all to an inverting{overscore (Q)} output), it is likely that some coefficients will changesign in progressing through the four phases, so some of the branches 614(624) in a particular group will be connected to non-inverting outputsof shift register 602 while other branches 614 (624) in the same groupare connected to inverting outputs of shift register 602.

The polyphase solution shown in FIG. 6 can be used in conjunction withresistive ladder networks as shown in FIGS. 3 and 6. In this case, it isnecessary to design four ladder networks, one for each sampling phase,but with each ladder network required to support only N/4 shift registertaps. The subsets of tap weights, when divided into four phases, willnot be left-right symmetrical so the ladder networks will not besymmetrical. Designing an asymmetrical ladder requires sorting all thecoefficients into ascending order of absolute value, as discussedearlier. Further, the four ladder networks corresponding to the fourchip or bit period phases should be designed to have the same outputimpedance, in case an external load is applied. This avoids the effectof an external load varying between the four phases. In a polyphasefilter, the final output conductance of all four ladders should be thesame. Therefore, it is necessary to scale the values in each ladder suchthat the final values of G_(O)′ are equal.

An exemplary embodiment of a 52-tap filter with an oversampling factorof 4 appears in Tables 1 and 2 below. The filter/converter in thisexample spans 13 bits or chips and is constructed in accordance with thepresent invention. The weights were picked from a symmetrical sin (x)/xresponse. The filter is implemented as a polyphase filter/converternetwork as in FIG. 6 but with the resistive ladder networks asillustrated in FIG. 3. Table 1 presents the filter tap coefficientscorresponding to each one of the four sampling phases.

TABLE 1 SIN(X)/X COEFFICIENTS BEFORE SORTING PHASE 1 PHASE 2 PHASE 3PHASE 4 −0.02294 −0.06454 −0.08887 −0.08608 −0.05409   0.00000   0.06106  0.10983   0.12836   0.10585   0.04289 −0.04697 −0.13927 −0.20387−0.21233 −0.14562   0.00000   0.21033   0.45500   0.69315   0.88206  0.98646   0.98646   0.88206   0.69315   0.45500   0.21033   0.00000−0.14562 −0.21233 −0.20387 −0.13927 −0.04697   0.04289   0.10585  0.12836   0.10983   0.06106   0.00000 −0.05409 −0.08608 −0.08887−0.06454 −0.02294   0.02192   0.05630   0.07073   0.06245

Table 2 presents the values for the resistive ladder network shunt andseries resistors, with one set of values for each of the four samplingphases. There are four sampling phases corresponding to four laddernetworks. Each ladder network employs sorted tap weights as describedabove. The four phases were symmetrically arranged about the sin(x)/xresponse, resulting in ladders 2 and 3 being identical apart from thetap connections and ladders 1 and 4 are also identical apart from thetap connections. Each of the above ladder networks must be providedtwice for each filter, connected to taps of the opposite polarity, whena balanced signal output is required for a balanced modulator.

TABLE 2 VALUES FOR RESISTIVE LADDER NETWORKS 1 . . . 4 SHUNT TAP THENSERIES RES TAP # LOGIC TO RES TO (OHMS) OUTPUT OUTPUT NODE (OHMS) NODEVALUES FOR PHASE 1 LADDER 10000.0 13 Q 1 465.1 2 10000.0 2 QBAR 2 5357.13 10000.0 10 QBAR 3 774.4 4 10000.0 3 QBAR 4 573.2 5 10000.0 1 Q 51134.0 6 10000.0 12 QBAR 6 806.5 7 10000.0 11 Q 7 458.5 8 10000.0 4 Q 8204.9 9 10000.0 5 QBAR 9 94.4 10 10000.0 9 QBAR 10 6697.4 11 10000.0 8 Q11 1250.5 12 10000.0 7 Q 12 — VALUES FOR PHASE 2 LADDER  9560.1 10 Q 12989.6 2  9560.1 13 Q 2 459.0 3  9560.1 11 Q 3 207.4 4  9560.1 2 QBAR 4263.2 5  9560.1 1 Q 5 586.7 6  9560.1 12 QBAR 6 422.3 7  9560.1 4 Q 71911.5 8  9560.1 5 QBAR 8 89.0 9  9560.1 6 Q 9 21.1 10  9560.1 9 QBAR 102077.3 11  9560.1 8 Q 11 3232.5 12  9560.1 7 Q 12 — VALUES FOR PHASE 3LADDER  9560.1 4 Q 1 2989.6 2  9560.1 1 Q 2 459.0 3  9560.1 3 Q 3 207.44  9560.1 12 QBAR 4 263.2 5  9560.1 13 Q 5 586.7 6  9560.1 2 QBAR 6422.3 7  9560.1 10 Q 7 1911.5 8  9560.1 9 QBAR 8 89.0 9  9560.1 8 Q 921.1 10  9560.1 5 QBAR 10 2077.3 11  9560.1 6 Q 11 3232.5 12  9560.1 7 Q12 — VALUES FOR PHASE 4 LADDER  1000.0 1 Q 1 465.1 2  1000.0 12 QBAR 25357.1 3  1000.0 4 QBAR 3 774.4 4  1000.0 11 QBAR 4 573.2 5  1000.0 13 Q5 1134.0 6  1000.0 2 QBAR 6 806.5 7  1000.0 3 Q 7 458.5 8  1000.0 10 Q 8204.9 9  1000.0 9 QBAR 9 94.4 10  1000.0 5 QBAR 10 6697.4 11  1000.0 6 Q11 1250.5 12  1000.0 7 Q 12 — —

When two ladder networks for two of the phases are identical, such asfor phases 2 and 3 above, an alternative to duplicating the laddernetworks is to use a single ladder network, and to switch the taps towhich it is connected to be the taps for phase 2, when phase 2 isselected to provide the output signal, then to be the taps for phase 3when it is time for phase 3 to provide the output signal. Thus only twodifferent ladder networks are needed to implement a four-phase filteroperating at four samples per chip, but each must be duplicated toprovide a balanced output. Thus a four-phase filter having a balancedoutput still requires two copies of each of two ladder networks, makingfour ladder networks in total. Each ladder network however comprisesonly one quarter the number of conductance values as described in U.S.Pat. No. 5,867,537, and so the net complexity and power consumption hasbeen reduced by applying the new invention of sorting the tap weightsinto absolute magnitude order in order to use a ladder network designproviding progressively greater attenuation of contribution fromsuccessive taps in sorted order.

The above-described circuits perform filtering of a continuous bitstreamprior to modulating a radio signal, in order to contain the spectrum ofthe radio transmission within an allocated channel. Some systems employdiscontinuous transmission where a transmission is started and stoppedat a regular or irregular rate. TDMA systems for example transmit onlyin an allocated time slot that recurs regularly within a TDMA frameperiod. Data systems likewise may transmit short data packets and thenawait a reply before transmitting the next packet. There is, therefore,a need to consider the start of transmission when a first informationbit is presented to the filter and modulator, no immediately prior bitsbeing present, and similarly at the end of transmission when no bitsfollow the last bit. A preferred method to start a transmission is toinitialize the transmit filter with zero bit values prior to inputtingthe first data bit, data bits being considered to have the non-zerovalues of +1 or −1. Thus the initial zero values successively becomereplaced by non-zero bit values as the first data bits are clocked in.

To represent data bit values as +1, −1 or zero, a ternary signal isrequired. A ternary signal can be represented by two bit-lines, one lineindicating the bit magnitude of zero (0) or non-zero (1) while the otherline indicates the bit sign (+or −). This can be done using two shiftregisters; one containing bit sign values and one containing bitmagnitude values. The data stream to be transmitted is applied to thetwo shift registers on two bit-lines as a stream of ternary values. Thedata stream begins with a preamble of at least N zero values, i.e. themagnitude value on the magnitude bit-line is set to zero and the zerosare clocked into the new, magnitude shift register. The bit polarity onthe bit sign-line is unimportant when the bit magnitude line is zero.The first non-zero bit to be transmitted is applied to the bit-sign linetogether with a ‘1’ on the bit magnitude line. Subsequent data bits areapplied to the bit sign line while holding the bit magnitude line at‘1’. After the last data bit has been input, the bit magnitude line isreturned to zero and held at zero for at least N bit periods to flushthrough the last bit of non-zero magnitude, returning the magnitudeshift register to the all zeros state.

When a non-zero bit exists in a particular register position, theappropriate ladder network tap shall be connected to the non-inverted(or inverted, if tap has a negative weight) output of the sign register.When a zero bit magnitude exists in the register however, the laddernetwork tap shall be taken to an intermediate value between Boolean ‘1’and Boolean ‘0,’ that is to a voltage of Vcc/2, where Vcc is the voltagelevel for a ‘1’ and ‘0’ is the voltage level for a ‘0’.

FIG. 7 shows an arrangement for switches 630 for selectively connectingthe ladder resistors indicated by G_(O) either to a predeterminednon-inverted or inverted output of the sign register, or alternativelyto a Vcc/2 line. Each switch 630 in FIG. 7 is a two-way switch comprisedof two pass-gates 732, 734, each pass-gate being formed with an N and aP FET back-to-back. A control line “Switch(n) ON” connects to the gateof the N-FET of the pass-gate 732 connected to the sign registernon-inverted or inverted output for tap (n), while the inverse controlline ‘Switch(n) OFF’ connects to the P-FET of the pass-gate 734. When“Switch(n) ON” is at a ‘1’ level and “Switch(n) OFF” is at a “0” level,both the N and the P-FETS of this pass-gate 732 become conductiveconnecting the ladder resistor to Q1 in this example. The control linesare connected to the other pass-gate 734 for switch(n) in swapped order,so that the second pass-gate 734, which connects to the Vcc/2 line, isin a high impedance state at this time.

When, however, the control polarities reverse, the first pass-gate 732turns OFF and the second pass-gate turns on to connect tap(n) to theVcc/2 line. The latter shall occur when the magnitude registercontrolling tap(n) contains a zero. In a polyphase filter operating withan oversampling factor greater than 1 and having therefore severalsampling phases with a pair of ladder networks associated with eachphase, the pass-gates 732, 734 shall connect all taps of a ladder toVcc/2 when that phase is deselected. Therefore the control line denotedby “Switch(n) ON” shall be formed from the logical AND of thephase-enable line and the selected bit of the magnitude register forcontrolling tap(n), which is in the example of FIG. 7, the magnitude bitassociated with sign bit 1 (Q1).

Likewise tap(n−1) is controlled by the second two-way switch shown inFIG. 7 in a like manner, using second control signals denoted by“Switch(n−1) ON” and “Switch(n−1) OFF” which are formed by the logicalAND of the phase-enable line and the magnitude register bit designatedto control tap(n−1), which in the example of FIG. 7 would be magnituderegister bit 3, as tap(n−1) is shown connecting to {overscore (Q)}(3).It will be recalled from the above discussion that sign bits are notnecessarily connected to like-numbered tap-resistors, but rather in anorder depending on the sorting of tap weights into magnitude order.Magnitude register bits are connected to control taps using this sameorder of connection.

The outputs of the switched-resistor ladder network for each phase maybe connected together. In a four-phase filter, three ladders of zerosignal contribution then load the single ladder phase that is enabled,resulting in an attenuation of the output voltage swing by a factor offour. The peak-to-peak voltage swing of each group of four ladders isthen from Vcc/2+Vcc/8 to Vcc/2−Vcc/8, a swing of Vcc/4. A second set offour ladders connected to the inverse sign-register outputs can providean output voltage swinging in the opposite sense to form a balancedsignal output of peak-to-peak swing of Vcc/2 between the two balancedoutputs. The attenuated swing is more than adequate to drive typicalbalanced mixers so there is no need to avoid the non-enabled phases fromloading the enabled phase in order to achieve a greater output signalswing.

In a balanced filter, it may also be noted that the Vcc/2 line is alwaysconnected to as many ladder taps of the inverse polarity as of thenon-inverted polarity, and therefore does not itself need to supply anysignal current. The Vcc/2 line does not, therefore, need to be aparticularly low impedance voltage source and can be formed as aresistive tap across the supply lines. When all phases are disabledbefore the start and after the end of transmission, all ladder taps areconnected to the Vcc/2 line that then determines the quiescent outputsignal voltage fed to the balanced modulator.

The complete block diagram for a 4-phase combined 52-tapfilter/converter including sign and magnitude registers and gates forcontrolling the ladder switches is shown in FIG. 8 and is generallyreferred to by the numeral 800. Note that the crisscrossedinterconnections between the ladders 820 and 830 and the output registertaps from the sign register 802 according to the aforementionedweight-magnitude sorted order have been omitted for clarity.

In general, an individual switch in switch block 808 is associated withan individual register tap in the sign register 802. In turn, theassociated individual register tap in the sign register 802 has acorresponding individual register tap in the magnitude register 804.When an individual register tap in the magnitude register 804 contains alogical “0,” the associated switch in switch block 808 connects a VCC/2reference signal to an associated input in one of the ladder networks820 or to an associated input in one of the complimentary laddernetworks 830. This VCC/2 connection is independent of the contents ofthe corresponding register tap in the sign register 802. Thus, thecontents—either a logical “0” or “1”—of an individual register tap inthe sign register 802 contribute nothing to either of the balancedoutputs 822 and 832 when the contents of the corresponding individualregister tap in magnitude register 804 contains a logical “0.”

When an individual register tap in the magnitude register 804 contains alogical “1,” the associated switch in switch block 808 connects itsassociated register tap output from the sign register 802 to anassociated input in one of the ladder networks 820 or to an associatedinput in one of the complimentary ladder networks 830. The associatedinput in the ladder networks 820 or 830 to which the register tap outputis connected through the switch depends on the state of the phaseenables signals input to the switch control logic 806—this is explainedin more detail later. Thus, individual register taps in the magnituderegister 804 individually enable corresponding individual register tapoutputs in the sign register 802 to connect with an associated input inone of the ladder networks 820 or complementary ladder networks 830.

In FIG. 8, a sign register 802 receives an input data stream comprisedof digital “1” and “0” values, with the sign register 802 clocked by abit rate clock whose frequency is matched to the bit rate period of theinput data stream. The sign register provides two sets of serial outputtaps taken from its internal register stages, one set being the logicalcomplement of the other. As earlier described, these two sets of outputtaps are interconnected with a block of switches 808. In this example,the bit rate clock is multiplied by a factor of four in the switchcontrol logic 806 to produce a switch clock synchronous with the bitrate clock but having four times the frequency—resulting in anoversampling factor M of four. This switch clock is used to clock a setof switch control signals that are output from the switch control logic806 to the block of switches 808.

A given output tap from the sign register 802 is associated with anindividual switch in the block of switches 808. Each bit rate period isdivided into four successive phases by the switch clock. The signregister 802 comprises L register stages, with L determined as thenumber of required filter taps N divided by the oversampling factor M.Thus, in this example, the number of sign register 802 output tapsL=52/4 or 13 taps—with each tap comprising a non-inverting and aninverting output. Each of the L register output taps in the signregister 802 has an associated weighting value for each of the fourphases, as determined by the filter tap weighting coefficients.

By applying four sets of weighting values to the 13 output taps, thecombined/filter converter has the equivalent of 52 taps (four phases perbit period times 13 taps). Each one of the four ladder networks 820 orcomplementary ladder networks 830 provide one of the four sets ofweighting values for the sign register 802 output taps. Switch controlsignals output from the switch control logic 806 cause the switches inswitch block 808 to synchronously switch in successive fashion throughall four ladder/complimentary ladder networks on a per-phase basis, eachphase time comprising ¼ of the input bit period. All switches in switchblock 808 are controlled coherently, so that all switches connect theirassociated register tap outputs to a phase 1 weight, then to a phase 2weight, and so on.

In summary, an individual switch in switch block 808 corresponds to aparticular register tap output from the sign register 802. Theindividual switch selectively connects its corresponding sign registertap to each one of four associated inputs in the ladder networks 820 and830 when the magnitude register tap corresponding to the switch'scorresponding sign register contains a logic “1.” In this condition, thebinary combination of phase enable signals determines which of the fourpossible ladder network inputs the switch selectively connects to. Whenan individual switch's associated magnitude register tap is a “0,” theswitch selectively connects one of its four associated ladder networkinputs to VCC/2. Again, the selective connection is made based on thephase enable signal input to the switch control logic 806.

Note that during a given phase, output 822 collectively corresponds to agiven set of inverting and non-inverting register tap outputs asweighted by ladder networks 820 and complimentary ladder networks 830.Output 832 represents the complement to output 822 and therefore itssignal changes will be antiphase with corresponding changes in the 822output. This complementary behavior of output 832 with respect to output822 is achieved by driving it with the set of register taps that arecomplementary to the set used to produce output 822. Of course, switchblock 808 and ladder networks 820 and 830 are connected such thatweighting factors applied to the complementary set of register taps areidentical with those used to produce output 822.

The foregoing explanation provides detailed representations for aspecific embodiment of the present invention. However, as will bereadily appreciated by those skilled in the art, the present inventionadmits tremendous flexibility in implementation. Further, the specificrealization of the present invention will depend on design requirements.Some systems will require greater or fewer register taps. Other systemsmay combine logical elements, illustrated separately here, intointegrated systems based on sophisticated microprocessors,application-specific-circuits (ASICs), field-programmable-gate-arrays,or other such integrated logic devices. All such variations in startingdesign parameters and physical circuit realization are considered to bewithin the scope of the present invention.

What is claimed is:
 1. A filter for filtering digitally quantized signalsamples with a desired filtering function to provide a filtered analogsignal, comprising: a memory device having a plurality of memoryelements for holding successive digital signal samples, each memoryelement having at least one associated signal output; a plurality ofcombining networks, each combining network comprising a plurality ofinputs corresponding to respective ones of said signal outputs and anoutput, wherein said outputs of said combining networks are combined toprovide said filtered analog output; and a selection circuit forselectively connecting selected signal outputs of said memory elementsto respective inputs of a selected one of said combining networks in apredetermined sequence during each of a plurality of signal samplingphases to provide said filtered analog signal at said output.
 2. Thefilter of claim 1 wherein said memory device is a shift register.
 3. Thefilter of claim 1 wherein said combining networks are resistivecombining networks having at least one weighting resistor associatedwith each of said inputs, and wherein the values of said weightingresistors are chosen based on a set of weighting coefficients thatdetermine said desired filtering function.
 4. The filter of claim 3wherein said at least one signal output includes a non-inverted outputand a complementary inverted output.
 5. The filter of claim 4 whereinsaid inputs of said combining network associated with a positiveweighting coefficient are connected to one of said non-inverted outputsand wherein said inputs of said combining network associated with anegative weighting coefficient are connected to one of said invertedoutputs.
 6. The filter of claim 3 wherein memory elements associatedwith a zero weighting coefficient are not connected to said combiningnetwork.
 7. The filter of claim 3 wherein each of said resistivecombining networks has the same electrical output impedance.
 8. Thefilter of claim 1 wherein said resistive combining networks are laddernetworks comprising a chain of series resistors and a plurality of shuntresistors, each shunt resistor being connected at one end to said chainof series resistors and at an opposite end to an associated one of saidinputs.
 9. The filter of claim 8 wherein each input of each saidcombining network has a characteristic attenuation determined by arespective one of said weighting coefficients.
 10. The filter of claim 9wherein each of said plurality of combining networks corresponds to asubset of said set of weighting coefficients.
 11. The filter of claim 10wherein said weighting coefficients in each of said subsets are sortedin order of absolute magnitude and associated in said sorted order withconsecutive ones of said inputs in said combining network.
 12. Thefilter of claim 1 wherein said selection circuit comprises one or moreswitches to sequentially connect said inputs of said plurality ofcombining networks to said signal outputs of said memory elements duringcorresponding signal sampling phases.
 13. The filter of claim 12 whereinsaid switches are CMOS bilateral switches using back-to-back P-type andN-type FETs.
 14. The filter of claim 12 wherein said switches connecteach of said inputs to a default electrical potential during signalsampling phases other than said corresponding signal sampling phase. 15.The filter of claim 1 wherein said at least one signal output comprisesa non-inverted output and an inverted output.
 16. The filter of claim 15wherein said plurality of combining networks comprise a first pluralityof combining networks, the inputs of which are sequentially connected toa first set of said inverted or non-inverted outputs, and a second,equal plurality of combining networks, the inputs of which are connectedto a second complementary set of said inverted and non-inverted outputs,wherein said outputs of said first plurality of combining networks arecombined at a first output and the outputs of said second plurality ofcombining networks are combined at a second output of said filteredsignal output thereby forming a balanced filtered analog signal.
 17. Thefilter of claim 1 wherein said digital signal samples are single-bitsamples.
 18. The filter of claim 1 wherein said digital signal samplesare ternary signal samples representing one of the values 1, 0, or −1.19. The filter of claim 18 wherein said ternary samples comprise twobits including a sign bit representing plus or minus and a magnitude bitrepresenting a zero or a non-zero magnitude.
 20. A filter for filteringdigitally quantized signal samples with a desired filtering function toprovide a filtered analog signal, comprising: a memory device having aplurality of memory elements for holding successive digital signalsamples, each memory element having at least one associated signaloutput; at least one resistive ladder network comprising an output and aplurality of inputs, each of said inputs in said combining networkhaving an associated weighting coefficient selected from a set ofdesired weighting coefficients that determine said desired filteringfunction, said inputs being arranged in sorted order based on theabsolute magnitude of said associated weighting coefficients; and eachof said signal outputs being connected to respective ones of said inputsbased on said weighting coefficients to provide said filtered analogsignal at said output.
 21. The filter of claim 20 wherein said memorydevice is a shift register.
 22. The filter of claim 20 wherein said atleast one resistive ladder network comprises a plurality of laddernetworks each associated with a sampling phase and with a correspondingsubset of said weighting coefficients.
 23. The filter of claim 22wherein said plurality of resistiveladder networks each have the sameelectrical output impedance, and said wherein said outputs from saidresistive ladder networks are combined to form said filtered analogsignal.
 24. The filter of claim 22 further comprising a switchingcircuit to sequentially select each of said plurality of resistiveladder networks during a corresponding sampling phase.
 25. The filter ofclaim 24 wherein said switching circuit comprises a set of switches toconnect said inputs to associated signal outputs of said memory elementsduring said corresponding sampling phase.
 26. The filter of claim 25wherein said switches connect said inputs to a default electricalpotential during sampling phases other than said corresponding samplingphase.
 27. The filter of claim 25 wherein said switches are CMOSbilateral switches using back-to-back P-type and N-type FETs.
 28. Thefilter of claim 20 wherein said at least one signal output comprises anon-inverted output and an inverted output.
 29. The filter of claim 28wherein said at least one resistive ladder network comprises a firstresistive ladder network with said inputs being connected to a first setof said inverted and non-inverted outputs of said memory elements and asecond, identical ladder network with said inputs connected to a secondcomplementary set of said inverted and non-inverted outputs of saidmemory elements.
 30. The filter of claim 29 wherein said output of saidfirst resistive ladder network and said output of said second resistiveladder network form a balanced output for said filtered analog signal.31. The filter of claim 28 wherein said at least one resistive laddernetwork comprises a first plurality of resistive ladder networks eachhaving inputs selectively connected to a first set of said inverted andnon-inverted outputs of said memory elements and a second, equalplurality of ladder networks each having inputs selectively connected toa second complementary set of said inverted and non-inverted outputs ofsaid memory elements, said outputs from said first plurality of laddernetworks being combined at a first output and said outputs of saidsecond plurality of ladder networks being combined at a second output toform a balanced filtered analog signal.
 32. The filter of claim 31wherein each of said first plurality of resistive ladder networks andthe corresponding identical one of said second plurality of resistiveladder networks are associated with a corresponding sampling phase andwith a corresponding subset of weighting coefficients.
 33. The filter ofclaim 32 further comprising a switching circuit to select said firstplurality of ladder networks and said corresponding second plurality ofladder networks in a predetermined sequence during a correspondingsampling phase to contribute to said filtered analog signal during thecorresponding sampling phase.
 34. The filter of claim 33 wherein saidswitching circuit comprises a set of switches to connect said inputs ofthe selected resistive ladder networks to corresponding signal outputsduring said corresponding sampling phase.
 35. The filter of claim 34wherein said switches further connect said inputs to a defaultelectrical potential during non-corresponding sampling phases.
 36. Thefilter of claim 35 wherein said switches are CMOS bilateral switchesduring back-to-back P-type and N-type FETs.
 37. The filter of claim 28wherein each of said inputs is connected to a corresponding one of saidnon-inverted outputs of said memory elements when said associatedweighting coefficient is positive, and to a corresponding one of saidinverted outputs of said memory elements when said associated weightingcoefficient is negative.
 38. The filter of claim 20 wherein said digitalsignal samples are single-bit samples.
 39. The filter of claim 20wherein said digital signal samples are ternary signal samplesrepresenting one of the values 1, 0, or −1.
 40. The filter of claim 39wherein said ternary samples comprise two bits including a sign bitrepresenting plus or minus and a magnitude bit representing a zero or anon-zero magnitude.
 41. The filter of claim 40 wherein said inputs ofsaid at least one resistive ladder network are each connected to saidoutputs of said memory device when said magnitude bit output is non-zeroand to a default electrical potential when said magnitude bit output iszero.
 42. A filter for smoothing blocks of digital signal samples with adesired filtering function prior to transmission to provide a filteredoutput signal, comprising: a memory device having a plurality of memoryelements for storing successive digital samples as a sign bitrepresenting a positive or negative signal sample sign and a magnitudebit representing a zero or a non-zero signal sample magnitude, eachmemory element having at least one signal output; at least one combiningnetwork having an output, said resistive combining network comprising aplurality of inputs connected to corresponding ones of said signaloutputs of said memory elements, wherein each input is selectivelyconnected to an associated signal output of a corresponding memoryelement when the associated magnitude bit is non-zero, and is connectedto a default electrical potential when said magnitude bit is zero. 43.The filter of claim 42 wherein said at least one signal output includesa non-inverted output and an inverted output.
 44. The filter of claim 43wherein said at least one combining network includes a first resistivecombining network selectively connected to a first set of saidnon-inverted and inverted outputs and a second resistive combiningnetwork selectively connected to a second set of said non-inverted andinverted outputs, said first and second resistive combining networkshaving a first and a second combined output forming a balanced outputfor said desired filtered signal output.
 45. The filter of claim 42wherein digital signal samples preceding and following said block ofdigital signal samples have a magnitude of zero and signal sampleswithin said block have a non-zero magnitude, thereby effecting a smoothramping up of the desired filtered signal output at the start of saidblock and a smooth ramping down of the filtered signal output at the endof said block.
 46. The filter of claim 42 wherein said at least onecombining network combines said digital signal samples with a pluralityof combining factors determined from said desired filtering function.47. The filter of claim 46 wherein said at least one combining networkis a resistive ladder network, each input having an associated weightingcoefficient selected from a set of weighting coefficients that determinesaid filtering function and being arranged in sorted order based on theabsolute value of said associated weighting coefficients.
 48. The filterof claim 42 wherein said at least one combining network comprises aplurality of resistive combining networks, said inputs of said pluralityof resistive combining networks being selectively connected toassociated signal outputs of said memory elements during a correspondingsignal sampling phase when the associated magnitude bit is non-zero, andbeing selectively connected to a default potential during anon-corresponding sampling phase or when said associated magnitude bitis zero.
 49. The filter of claim 48 wherein said outputs of saidplurality of combining networks are combined to form the desiredfiltered output signal.
 50. The filter of claim 47 including a pluralityof ladder networks, wherein said input of each said resistive laddernetwork is selectively connected to said signal output of acorresponding memory element during a corresponding signal samplingphase when the associated magnitude bit is non-zero, and to a defaultpotential when the associated magnitude bit is zero.
 51. The filter ofclaim 50 wherein each of said resistive ladder networks have the sameoutput impedance.
 52. The filter of claim 43 wherein said at least oneresistive combining network combines said digital signal samples using aplurality of combining factors given by a set of weighting coefficientsthat determine said desired filtering function to provide said filteredanalog signal.
 53. The filter of claim 52 wherein said inputs of said atleast one resistive combining network having positive associatedweighting coefficient are selectively connected to said non-invertedoutputs of said memory elements and inputs having a negative associatedweighting coefficient are selectively connected to inverted outputs ofsaid memory elements.
 54. The filter of claim 53 wherein said at leastone resistive combining ladder network comprises a first ladder networkhaving inputs connected to a first set of said non-inverted and invertedoutputs of said memory elements, and a second ladder network havinginputs connected to a second set of said non-inverted and invertedoutputs of said memory elements.
 55. The filter of claim 50 wherein eachsaid input is connected to a default potential during sampling phasesother than said corresponding sampling phase.
 56. The filter of claim 51wherein each said ladder network provides said desired filtered outputsignal during a corresponding sampling phase.
 57. A method of filteringdigital signal samples with a desired filtering function to provide afiltered analog signal, said method comprising: serially inputting,during a plurality of successive signal sampling phases, successivedigital signal samples into a memory device having a plurality of memoryelements, each memory element having at least one signal output;connecting said signal outputs of said memory elements to a selected oneof a plurality of combining networks during each of said successivesignal sampling phases, each of said combining networks providing anoutput during a corresponding signal sampling phase; and combining saidoutputs of said combining networks during said successive signalsampling intervals to provide said filtered analog signal.
 58. Themethod of claim 57 wherein said combining networks are resistivenetworks having a plurality of inputs, each input having an associatedweighting resistor, wherein the values of said weighting resistors areselected based a set of weighting coefficients that determine saiddesired filtering function.
 59. The method of claim 58 wherein said atleast one signal output includes a non-inverted output and acomplementary inverted output.
 60. The method of claim 59 wherein saidinputs of said resistive networks associated with a positive weightingcoefficient are connected to one of said non-inverted outputs andwherein said inputs of said combining network associated with a negativeweighting coefficient are connected to one of said inverted signoutputs.
 61. The method of claim 57 wherein said resistive combiningnetworks are resistive ladder networks comprising a chain of seriesresistors and a plurality of shunt resistors, each shunt resistor beingconnected at one end to said chain of series resistors and at anopposite end to an associated one of said plurality of inputs.
 62. Themethod of claim 61 wherein said series and shunt resistors provide aplurality of attenuation factors each corresponding to a weightingcoefficient selected from a set of weighting coefficients that determinesaid desired filtering function.
 63. The method of claim 57 wherein eachof said plurality of combining networks corresponds to a subset of saidset of weighting coefficients.
 64. The method of claim 63 wherein saidweighting coefficients in each of said subsets are sorted in order ofabsolute magnitude and associated in said sorted order with consecutiveones of said inputs in said combining network.
 65. The method of claim57 wherein said at least one signal output comprises a non-invertedoutput and an inverted output.
 66. The method of claim 65 wherein saidplurality of combining networks comprise a first plurality of combiningnetworks having a plurality of inputs connected to a first set of saidinverted or non-inverted outputs, and a second, equal plurality ofcombining networks having inputs connected to a second set of saidinverted or non-inverted outputs, wherein the outputs of said firstplurality of combining networks are combined at a first output and theoutputs of said second plurality of combining networks are combined at asecond output thereby forming a balanced signal output.
 67. A method offiltering digital signal samples, each sample represented by a sign bitand a magnitude bit, with a desired filtering function to provide afiltered analog signal, said method comprising: serially inputting amagnitude bit stream comprising a plurality of said magnitude bits intoa magnitude register having a plurality of memory elements; seriallyinputting a corresponding sign bit stream comprising a plurality of saidsign bits into a sign register having a plurality of memory elements;connecting said memory elements in said sign register to respectiveinputs of at least one combining network when a corresponding bit insaid magnitude bit register is non-zero; and combining signals presentat said inputs of said combining network to provide said filtered analogsignal at an output of said combining network.
 68. The method of claim67 wherein said memory elements in said sign register include aninverted and a non-inverted output, and wherein said step of connectingsaid memory elements in said sign register to said at least onecombining network comprises selectively connecting a first set of saidinverted and non-inverted outputs to inputs of a first combining networkand selectively connecting a second complementary set of said invertedand non-inverted outputs to inputs of a second combining network to forma balanced output for said filtered analog signal.
 69. The method ofclaim 67 wherein said step of combining said signals present at saidinputs of said combining network comprises weighting said signalspresent at said inputs with a set of weighting coefficients thatdetermine said desired filtering function.
 70. The method of claim 69wherein said combining network comprises a resistive ladder networkhaving a plurality of inputs, each input having an attenuationcorresponding to an associated one of said weighting coefficients. 71.The method of claim 70 wherein said inputs of said resistive laddernetwork are arranged in sorted order based on absolute values of saidassociated weighting coefficients.
 72. The method of claim 67 whereinsaid at least one combining network comprises a plurality of combiningnetworks, each corresponding to one of a plurality of signal samplingphases, and wherein said step of connecting said memory elements in saidsign register to said at least one combining network comprisessequentially connecting said plurality of signal outputs of said memoryelements to a corresponding one of said combining networks during eachof said signal sampling phases.
 73. The method of claim 72 wherein saidmemory elements in said sign register include an inverted and anon-inverted output, and wherein said step of connecting said memoryelements in said sign register to said at least one combining networkfurther comprises connecting a first set of said inverted andnon-inverted outputs to inputs of a first combining network andconnecting a second complementary set of said inverted and non-invertedoutputs to inputs of a second combining network to form a balancedoutput for said filtered analog signal.
 74. A method of filteringdigital signal samples with a desired filtering function to provide afiltered analog signal, said method comprising: inputting successivedigital signal samples into a serial memory device having a plurality ofmemory elements, each memory element having at least one output signalassociated with one of a set of weighting coefficients determined bysaid desired filtering function; connecting selected ones of said outputsignals of said memory elements to respective inputs of at least onecombining network, each one of said inputs having an attenuation withrespect to a common output corresponding to one of said set of weightingcoefficients, said inputs arranged in order based on the absolutemagnitude of said corresponding weighting coefficients; combining saidplurality of output signals in said combining network to produce saidfiltered analog signal at said common output.
 75. The method of claim 74wherein said at least one combining network comprises a plurality ofcombining networks corresponding to a plurality of digital signalsampling phases and wherein said connecting step further comprisesselectively connecting selected output signals of said memory elementsto a corresponding one of said plurality of combining networks duringeach of said digital signal sampling phases.
 76. The method of claim 75wherein said at least one output signal from each said memory element insaid memory device includes an inverted and non-inverted output signal,and wherein said connecting step further comprises connecting a firstset of said inverted and non-inverted output signals to a firstcombining network and connecting a second complementary set of saidinverted and non-inverted output signals to a second combining networkto form a balanced output for said filtered analog signal.
 77. Themethod of claim 74 wherein said at least one output signal from eachsaid memory element in said memory device includes an inverted andnon-inverted output signal, and wherein said connecting step furthercomprises connecting a first set of said inverted and non-invertedoutput signals to a first combining network and connecting a secondcomplementary set of said inverted and non-inverted output signals to asecond combining network to form a balanced output for said filteredanalog signal.
 78. A combined digital-to-analog conversion and filteringcircuit to convert a digital signal into an analog signal filteredaccording to a desired filter function comprising: a resistive laddernetwork comprising a plurality of weighted tap inputs coupled to acombined signal output through a network of weighting resistorsdetermined from tap coefficients of a desired digital filter, andwherein the weighted tap inputs are ordered according to tap coefficientmagnitude; and a digital shift register to successively shift samples ofthe digital signal through a plurality of successive stages, each stageincluding at least one digital output, and wherein the digital outputsfrom one or more stages are coupled to the corresponding ones of theweighted tap inputs of the resistive ladder network in accordance withthe desired filter function.
 79. A method of simultaneously filteringand converting a digital signal to an analog signal comprising: defininga plurality of weighting factors, or tap coefficients, in accordancewith a desired filter function; defining a plurality of weightingresistors, corresponding to the plurality of weighting factors, within aresistive ladder network with a plurality of weighted tap inputs and acombined signal output; coupling digital outputs from one or more stagesin a digital shift register to the corresponding plurality of weightedtap inputs of the resistive ladder network in accordance with thedesired filter function; and shifting successive digital signal samplesthrough the digital shift register, such that a filtered analog signalis formed at the combined signal output of the resistive ladder network.